Careers > Enhance Processor-in-the-Loop (PIL) capabilities in QGen
Last modified 9/30/2021 9:58:46 AM

Enhance Processor-in-the-Loop (PIL) capabilities in QGen

Internship
AdaCore
Paris, France or Tallinn, Estonia
Bac + 4/5

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Enhance Processor-in-the-Loop (PIL) capabilities in QGen

 

Context:

Simulating and debugging embedded code may need to execute at least a part of the code on the final embedded device. When the code comes from a Simulink/Stateflow model, it is very convenient to execute a part or all the model within the final hardware.

We would like to enhance the PIL capabilities of QGen (automatic code generator from Simulink/Stateflow) to facilitate execution on the hardware (or simulators) of the code generated using the debugger (gdb) to communicate the Simulink simulation environment with the target hardware.

The goal of this internship is to extend the existing capabilities to simplify customer’s workflow when integrating or debugging Simulink/Stateflow models that are intended to execute on embedded hardware.

 

Goals:

  • Understand the ways to interact with the Simulink simulation environment 

  • Define and discuss the design and the workflow

  • Implement and test the chosen solution, and integrate it within the product

 

Skills required or Nice to have:

  • Familiarity with one high-level object-oriented programming language (Ada, C++, Java)

  • Familiarity with embedded systems

  • Familiarity with gdb debugger

  • As a bonus, familiarity with Simulink/Stateflow

  • Ability to learn quickly about new development practices

 

 

Timeframe and location:

  • Time scale flexible, ideally in 2022

  • Duration somewhat flexible, ideally 6 months

  • Location: Paris (France), Tallinn (Estonia)

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